1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and method of manufacturing the same. In particular, the invention relates to technology that can be effectively applied to a semiconductor integrated circuit device having a DRAM (dynamic random access memory).
2. Prior Art
Memory cells in a DRAM are arranged at intersecting points of plural word lines and plural bit lines arranged in the form of a matrix on the main surface of a semiconductor substrate, and are each constituted by a memory cell-selecting MISFET and a data-storing capacitor element (capacitor) connected in series therewith.
The memory cell-selecting MISFET constituting a portion of the memory cell is formed chiefly by a gate oxide film, a gate electrode constituted integrally with a word line, and a pair of semiconductor regions constituting a source and a drain. Further, the data-storing capacitor element constituting another portion of the memory cell is arranged on the memory cell-selecting MISFET, and is electrically connected to either the source or the drain.
A bit line electrically connected to the other one of the source or the drain of the memory cell-selecting MISFET is usually arranged between the memory cell-selecting MISFET and the data-storing capacitor element. This is because, when it is attempted to increase the amount of electric charge stored in the data-storing capacitor element, the surface area must be increased by realizing a three-dimensional structure. When a bit line is arranged on the data-storing capacitor element of the three-dimensional structure, the aspect ratio of the contact hole connecting the bit line to the memory cell-selecting MISFET becomes very great, making it difficult to open a hole.
International Laid-Open Publication WO98/59372 (U.S. Ser. No. 09/446,302) discloses a DRAM in which a bit line is arranged between a memory cell-selecting MISFET and a data-storing capacitor element, and a method of producing the same.
A bit line of the DRAM disclosed in the above publication has a width which is narrower than a gap to a neighboring bit line in order to lower the parasitic capacitance among the bit lines, that becomes conspicuous when a memory cell is realized in a very small size.
Further, the bit line is constituted by a metal film formed chiefly of W (tungsten). By forming the bit line using a metal film of a low resistance, it is allowed to decrease the sheet resistance and, hence, to increase the speed for reading and writing data. It is further allowed to simultaneously form a metal wiring of a peripheral circuit of the DRAM in the step of forming bit lines, making it possible to simplify the step of producing the DRAMs. Besides, tungsten exhibits a larger resistance against the electromigration than aluminum, and makes it possible to decrease breakage in the line when the width of the bit line is very decreased.
The bit line is electrically connected to either the source or the drain of the memory cell-selecting MISFET through a hole formed in the silicon oxide film (second silicon oxide film) and a contact hole formed in the silicon oxide film which is the lower layer (first silicon oxide film). A plug of a polycrystalline silicon film having a low resistance is buried in the contact hole formed in the first silicon oxide film.
The bit line is formed roughly through the following process. First, a MISFET (memory cell-selecting MISFET) constituting a memory cell and MISFETs (n-channel MISFET and p-channel MISFET) constituting a peripheral circuit are formed on a semiconductor substrate. Then, a first silicon oxide film is formed over these MISFETs, and contact holes are formed in the first silicon oxide film over the source and drain of the memory cell-selecting MISFET. One of these contact holes is used for connecting either one of the source or the drain to the bit line, and the other one is used for connecting the other one of the source or the drain to the data-storing capacitor element.
Next, a polycrystalline silicon film doped with n-type impurities (e.g., P (phosphorus)) is deposited on the first silicon oxide film and, then, unnecessary polycrystalline silicon film on the silicon oxide film is removed to form a plug in the contact hole.
Next, a second silicon oxide film is formed on the first silicon oxide film, and a through hole is formed in the second silicon oxide film on one of the contact holes (contact hole to which the bit line is connected). The second silicon oxide film is formed for maintaining electric insulation between the bit line and the plug in the other contact hole (contact hole to which the data-storing capacitor element is connected).
Next, the tungsten film is formed on the second silicon oxide film that includes a region over the through hole, and is then patterned to form a bit line. Here, however, when the bit line formed of tungsten film comes into direct contact with the plug (polycrystalline silicon film) in the contact hole, a silicide layer having a high electric resistance is formed on the interface between the two. Therefore, a barrier film such as TiN (titanium nitride) is formed between the bit line (W film) and the plug (polycrystalline silicon film) to prevent the interfacial reaction between them. That is, in a practical step of forming bit lines, a TiN film is, first, formed on the second silicon oxide film inclusive of an upper region of the through hole and, then, the tungsten film is formed on the TiN film. Thereafter, the tungsten film and the TiN film are patterned by dry-etching by using a photoresist film as a mask to form bit lines.
The TiN film has an electric resistance larger than that of the W film. It is therefore desired that the TiN film has a small thickness from the standpoint of decreasing parasitic resistance. Besides, the contact resistance between the TiN film and the polycrystalline silicon film is greater than that of between the TiN film and the W film. From the standpoint of decreasing the parasitic resistance, therefore, it is better that the contact area is great between the TiN film and the polycrystalline silicon film.
Further, the TiN film has a large stress. Therefore, if the thickness of the film is increased, voids develop between the TiN film and the polycrystalline silicon film due to stress possessed by the TiN film, and the interface between the TiN film and the polycrystalline silicon film is completely peeled off. From the standpoint of decreasing the stress in the TiN film, it is desired that the thickness of the TiN film is small. Further, even if voids have developed to some extent, the structure must be such that a reliable connection is maintained between the TiN film and the polycrystalline silicon film.
However, the source of memory cell-selecting MISFET and the diameter of the contact hole formed on the drain are becoming ever small accompanying an increase in the degree of integration, and the aspect ratio of the contact hole is becoming ever large.
In the above-mentioned DRAM of the prior art, further, the width of the bit line is becoming narrower than the diameters of the contact hole and the through hole through which the bit line is connected to the memory cell-selecting MISFET as a result of considerably decreasing the width of the bit line for decreasing the size of the memory cell.
When the width of the bit line constituted by a laminate of the TiN film and the W film is considerably decreased, the contact area between the plug buried in the contact hole and the bit line formed thereon decreases in proportion thereto. Here, the polycrystalline silicon film constituting the plug has its interface contacted to the TiN film that constitutes the lower layer of the bit line. As the contact area between the bit line and the plug decreases, however, the contact resistance greatly increases between the bit line and the plug. Further, voids occur in the interface between them due to contraction of volume of the TiN film caused by the heat treatment executed in the step of production, whereby the contact resistance further increases between the two and, in an extreme case, a defect occurs in that the bit line peels off the surface of the plug.
Further, according to the prior art of forming bit lines by dry-etching the laminate of the TiN film and the W film, it becomes difficult to maintain the etching selection ratio for the polycrystalline silicon film and the TiN film constituting the plug, and the surface of the plug (polycrystalline silicon film) is deeply etched during the patterning of the bit lines.
In the above-mentioned DRAM of the prior art, further, the contact hole is formed in the first silicon oxide film to bury the plug therein and, then, the second silicon oxide film is formed on the first silicon oxide film, and the through hole is formed in the second silicon oxide film on one of the contact holes (contact hole to which the bit line is connected), causing the steps to become complex. Such an increase in the number of steps becomes a problem particularly in the DRAM in which the metal wiring of the peripheral circuit is simultaneously formed in the step of forming the bit lines, and in the DRAM-logic hybrid LSI in which the metal wiring of the logic circuit is simultaneously formed in the step of forming the bit lines.
It is an object of the present invention to provide technology related to a DRAM forming bit lines on the plugs constituted by a polycrystalline silicon film via a barrier layer, decreasing the contact resistance and improving reliability in the connection by preventing a reduction in the contact area between the plug and the barrier layer.
Another object of the present invention is to provide technology capable of decreasing the number of the steps for producing a DRAM forming bit lines on the plugs constituted by a polycrystalline silicon film via a barrier layer, or a hybrid LSI including the DRAM.
The above and other objects as well as novel features of the present invention will become obvious from the description of the specification and the accompanying drawings.
Briefly described below are representative examples of the inventions disclosed in this application.
(1) A semiconductor integrated circuit device according to the invention comprises:
a first insulating film formed on a first MISFET in a first region and on a second MISFET in a second region on the main surface of a semiconductor substrate;
a first plug electrically connected to either the source or the drain of the first MISFET and a second plug formed on the first plug, the first and second plugs being buried in a first connection hole formed in the first insulating film in the first region;
a third plug electrically connected to either the source or the drain of the second MISFET, the third plug being buried in the second connection hole formed in the first insulating film in the second region; and
a first wiring formed on the first insulating film in the first region, the first wiring being electrically connected to either the source or the drain of the first MISFET via the first plug and the second plug in the first connection hole; wherein
the second plug in the first connection hole is constituted by a first metal film of a first metal material and a second metal film of a second metal material formed thereon; and
the third plug in the second connection hole is constituted by a third metal film of the first metal material and a fourth metal film of the second metal material formed thereon.
(2) A method of manufacturing a semiconductor integrated circuit device of the invention comprises the steps of:
(a) forming a first MISFET in a first region on the main surface of a semiconductor substrate, forming a second MISFET in a second region, and forming a first insulating film on the first MISFET and on the second MISFET on the main surface of the semiconductor substrate;
(b) forming a first connection hole in the first insulating film in the first region, and burying a first plug in the first connection hole to electrically connect the first plug to either one of the source or the drain of the first MISFET;
(c) forming a second connection hole in the first insulating film in the second region, burying a second plug on the first plug in the first connection hole in a manner that the first plug and the second plug are electrically connected together, and burying a third plug in the second connection hole so as to be electrically connected to either the source or the drain of the second MISFET; and
(d) forming a first wiring on the first insulating film in the first region, and electrically connecting either the source or the drain of the first MISFET to the first wiring through the first plug and the second plug in the first connection hole.